Capping coating for 3D integration applications

ABSTRACT

A structure for a semiconductor component is provided having a bi-layer capping coating integrated and built on supporting layer to be transferred. The bi-layer capping protects the layer to be transferred from possible degradation resulting from the attachment and removal processes of the carrier assembly used for layer transfer. A wafer-level layer transfer process using this structure is enabled to create three-dimensional integrated circuits.

RELATED APPLICATIONS

[0001] This application claims benefit of U.S. Provisional Application60/444, 502, filed Feb. 3, 2003, entitled “Silicon Nitride/A110 CappingBi-Layer in Copper-Polyimide Systems for 3 D Integration Applications”.

FIELD OF THE INVENTION

[0002] The present invention relates to the integration of circuitcomponents into a 3 D structure using a wafer-level layer transferprocess based on the incorporation of capping bi-layers for reliableconnection of integrated circuits, components, and other semiconductorcomponents.

BACKGROUND OF THE INVENTION AND DESCRIPTION OF THE PRIOR ART

[0003] In recent years, a variety of three-dimensional (3 D) integrationand packaging techniques have been examined. The main considerationsbehind the use of 3 D integration are: 1) minimization of the wirelength, 2) incorporation of new back-end-of-the-line (BEOL) processesthat are currently limited by conventional planar technology, and 3)implementation of related design flexibility. Items 1-3 mentioned abovewould allow significantly reduced interconnect delay as well as acomplex system integration to increase both performance andfunctionality.

[0004] Approaches to 3 D integration at either the chip or wafer levelhave been described in the prior art. For example, wafer level bondingcan be achieved via an assembly approach. In such a method, layers aretransferred one by one, on top of each other, and attached by a bondingprocess. The prior art layer transfer process is realized using carrierwafers, most often a glass substrate.

[0005] In such a scheme, the glass substrate is attached to thestructure by an adhesive bonding process and released after the layertransfer is completed. One of the methods to release glass is based onlaser ablation, which entails irradiating the glass/adhesive interfacethrough the back surface of the glass substrate. In order to accomplishthe ablation process, polyimide materials are typically used as asacrificial adhesive layer in prior art 3 D integration schemes. Thepolyimide sacrificial adhesive layers are deposited on top of the layerthat will be subsequently transferred. During ablation, the depositedenergy is contained within a shallow (submicron) surface layer for anapproximate 50 ns duration of the excimer laser pulse due to thepolyimides strong absorption properties of ultraviolet laser radiationand poor thermal conductivity. When the absorbed energy density exceedsa certain threshold value, a surface layer having a thickness of lessthan 1 μm is photo-ablated and the laser separation of the glass carriersubstrate is realized. The laser ablation process using polyimides hasbeen reported and a comprehensive summary has been provided bySrinivasan, et al., “Ultraviolet Laser Ablation of Organic Polymers”,Chem. Rev. 990, 1303-1316 (1989).

[0006] The assembly approach in which laser ablation is used is only oneof the examples in which the polyimide material is used in a 3 Dintegration scheme. In general, in 3 D structures, the polyimide layeris deposited on an already processed and tested device layer terminatedwith at least one Cu-based wiring layer. When a polyamic acid (PAA)solution, which is the precursor for the formation of polyimide films,is spin applied to the Cu surface and subsequently cured at atemperature between 350′-400° C., Cu reacts with the polyamic acidduring the curing step to form salts which diffuse into the polyimidelayer to form copper oxide precipitates. This is disclosed, for example,in Kim, et al., “Adhesion and Interface Investigation of Polyimides onMetals”, J. Adhesion Sci. Technol., Vol. 2, No. 2, pp. 95-105 (1988). Asdemonstrated by Kowalczyk, et al., “Polyimide in Copper: The Role ofSolvent in the Formation of Copper Precipitates”, Appl. Phys. Lett.,Vol. 52, No. 5, pp. 375-376, (1988), the polyimide precursor solvent,n-methyl pyrrolidone (NMP), provides mobility for the aggregation of Cuprecipitates.

[0007] This situation is worsened when photosensitive polyimides areused since reacted Cu leaves a residue upon development, which is verydifficult to clean; see, in this regard, Perfecto, et al. “Evaluation ofCu Capping Alternatives for Polyimide-Cu MCM-D”, ECT. '01 (2001). In thecase of a preimidized polyimide, Cu diffusion has been observed anddocumented in U.S. Pat. No. 5,081,005. Over the years, thecopper-polyimide interface has been well studied. Copper-polyimidetechnology has been successfully used in the form of multi-level thinfilm structures for over two decades now. It has been primarilydeveloped for use in the cost/performance SCM's and high end MCM'sapplications; see, for example, Prasad, et al., “Multilevel Thin FilmApplications and Processes for High and Systems”, IEEE Transactions andComponents, Packaging, and Manufacturing Technology-Part B, Vol. 17, No.1, pp. 38-49 (1994).

[0008] In these applications, to prevent copper diffusion into thepolyimide, various metal capping layers have been used. Illustrativeexamples of prior art polyimide capping layers include, for example, Cr,Pt, Pd, Ti, Co (P), and chromate treatment; see, in this regardMatienzo, et al., “Adhesion of Metal to Polyimides, in Polyimides:fundamentals and applications”, K. K. Ghosh and K. L. Mittal Eds.,Marcel Dekker, NY, N. Y. (1996); Shih, et al., “Cu passivation: a methodof inhibiting copper-polyamic acid interactions”, Appl. Phys. Lett.,Vol. 59, No. 12, pp. 1424-1426 (1991); Ohuchi, et al., “SummaryAbstract: Ti as a diffusion barrier between Cu and polyimide”, J. Vac.Sci. Technol. A, Vol. 6, No. 3, pp. 1004-1006 (1988); O'Sullivan, etal., “Electrolessly deposited diffusion barriers for microelectronics”,IBM J. Res. Develop., Vol. 42, No. 5, pp. 607-619 (1998).

[0009] Also, baseline requirements for a capping layer in theCu-polyimide system used for various packaging structures have beenestablished. Namely, any Cu passivation metal should be chemically inertand insoluble in PAA; and the passivation metal should be a gooddiffusion barrier against Cu outdiffusion at temperatures less than 100°C. when the solvent NMP is present (above this temperature the Cutransports into the polyimide via solid-state-diffusion). Moreover, thepassivation metal should not diffuse into Cu to cause resistivityincrease.

[0010] In addition to copper diffusion barrier properties, metal capswere found to enhance adhesion between Cu and a polyimide. Theshortcoming of this Cu/metal cap/polyimide is based on the processinglimitation, for example, when the metal wiring is defined by thesubtractive etching of a Cr/Cu/Cr sputtered film, Cr protection onlyoccurs on the top of the wiring. Similar problems take place when ametal is deposited by a lift-off process. Hence, this solution has beenlimited to pattern electroplated films, where Co or chromate treatmentshave been shown to successfully encapsulate the Cu wiring.

[0011] However, in case of 3 D integration applications, the concernabout metal capping layers is based on compatibility of these materialswith various heterogeneous structures involved in future 3 D integrationschemes. The capping could be introduced as a continuous layer acrossthe whole wafer. In this case, after the layer transfer and ablation ofthe glass substrate is completed, this layer would be exposed to theremoval of the polyimide (the removal step is not present in theaforementioned packaging applications). Wet and dry methods have beenused to remove polyimides, but oxygen-plasma based removal has beenproven most effective, and it is also is a well understood process.

[0012] Therefore, in case of 3 D structures, requirement of goodCu-diffusion barrier (specially against activated oxygen in a plasmaetching environment) is additionally mandated of the capping layer.Since titanium is prone to oxidation in an oxygen-plasma, it cannot beconsidered as a candidate for a capping layer. Even if other cappingmetal candidates are stable in the oxygen-plasma environment, once thepolyimide stripping process has been completed, the additional step ofremoving the sacrificial capping layer would have to be implemented inorder to provide electrical separation between Cu wires. This removalprocess needs to be CMOS compatible, and preserve the structural,mechanical and electrical stability of the underlying patternedstructures. Selective etching of such capping metals without degrading(etching or damaging) the underlying copper wires makes the choice ofsuch a metal cap layer even more difficult. Taking all theserestrictions into consideration, the metal capping-sacrificial coatingof a full wafer is not likely to be feasible from the manufacturingpoint of view.

[0013] The metal capping in the form of a selective cap, such aselectroless Co on the top of Cu structures, could be implemented in a 3D integration scheme. However, application of such a cap will belimited, as 3 D structures may implement various heterogeneous materialsand their compatibility with Co, or other relevant selective metal capswould have to be established.

[0014] The organic copper-capping technology for the Cu-polyimide systemwas also developed for thin film packaging. It has been shown that athin organic coating, such as poly(arylene ether benzimidazole) (PAEBI),silane-modified polyvinylimidazole, or polybenzimidazole, can be applieddirectly to a wiring layer for enhancing adhesion to both the copperwiring and the polymer dielectric surface. These materials provide 100%protection for copper wiring, eliminating the need for metal capping,but at the expense of adding a thermal treatment step prior to thecoating of the polyimide. This is described, for example, in Lee, etal., “Adhesion of poly (arylene ether benzimidazole) to copper andpolyimides”, J. Adhesion Sci. Technol., Vol. 10, No. 9, pp. 807-821(1996); and Ishida, et al., “Modified Imidazoles: degradation inhibitorsand adhesion promoters for polyimide films on copper substrates”, J.Adhesion, Vol. 36, pp. 177-191 (1991). Such predominantly organic capswill be attacked by oxygen plasma exposure and will not protect thecopper wires during the post ablation cleaning step of plasma ashing.

[0015] Organic caps that do not require additional thermal treatmentshave been evaluated by Perfecto, et al., “Evaluation of Cu cappingalternatives for cu-Cu MCM-D, ECTC'01 (2001).

[0016] Two approaches were investigated in the Perfecto, et al.paper: 1) re-formulation of the PAA with an additive which will reducethe Cu diffusion and/or prevent Cu from complexing with the PAA, and 2)spun dry precoat of a Cu surface with an organic solution that reactswith Cu reducing the availability of Cu for diffusion. In the firstmethod, 1% tetrazole in a polyimide solution, and 5% benzotriazole (BTA)in a polyimide solution were evaluated, while in the second method anamino silane, namely, 3-aminopropyl-trimethoxy silane diluted to 1% indeionized water, as well as BTA diluted to 1% NMP were studied. Allsystems showed degraded performance when compared to the simplest andmost robust process of coating copper with 3-aminopropyl-trimethoxysilane. A layer of 3-aminopropyl-trimethoxy silane exhibited superiorperformance as an adhesion promoter in the Cu-polyimide system, and as aCu-diffusion limiting layer, and its use as a capping layer inpackage-related applications has been described in U.S. Pat. Nos.5,081,005 and 5, 194,928.

[0017] However, a coating of 3-aminopropyl-trimethoxy silane (usually afew monolayers) is not stable in the plasma-environment, and hence itcannot serve as an oxygen-diffusion barrier. Therefore, its use as acapping layer in the 3 D integration applications is limited to schemeswhen no oxygen-plasma processes are involved. However, othercharacteristics of 3-aminopropyl-trimethoxy silane, such as its abilityto promote interfacial strength in both polyimide/silicon dioxide andsilicon/silicon nitride laminates, make this system a great candidate inthe scheme for capping layer discussed below.

[0018] In view of the above, there is a need for providing an improvedcapping layer which provides adhesion as well as protection tounderlying layers such as metal-based semiconductor elements.

SUMMARY OF THE INVENTION

[0019] The present invention relates to the three-dimensionalintegration of semiconductor elements, such as devices andinterconnections, using a novel layer transfer process. Moreover, thepresent invention overcomes the difficulties associated with theintegration of various materials and devices through the use of apassivation capping coating to protect the underlying metal-basedsemiconductor elements. The inventive process provides a wafer-levellayer transfer that is compatible with CMOS technology and enablesintegration of various active, passive and interconnecting circuitelements.

[0020] In particular, it is an object of this invention to provide asupporting structure for an integrated 3 D interconnect circuit for highfrequency and high speed computing applications.

[0021] It is a further object of the present invention to combine theknow-how of layer transfer technology to form a complete high densityinterconnect structure with integrated functional components.

[0022] It is a still further object of this invention to enable a lowcost of ownership process based on a bi-layer capping coating using anadhesive component and a diffusion barrier component.

[0023] Specifically, and in broad terms, the present invention providesa structure for interconnecting semiconductor components comprising:

[0024] a layered substrate including, for example, semiconductorcomponents, for transferring;

[0025] a bi-layer capping coating on top of the substrate, each layer ofsaid coating provides adhesion and protection; and

[0026] a carrier assembly.

[0027] The inventive structure can be used for interconnecting varioussemiconductor components including, for example, semiconductor devices,semiconductor circuits, thin film layers, passive and/or activeelements, interconnect elements, memory elements,micro-electro-mechanical elements, optical elements, optoelectronicelements, and photonic elements.

[0028] In addition to the above-mentioned structure, the presentinvention also provides a method for fabricating the same. Specifically,and in broad terms, the method of the present invention comprises thesteps of:

[0029] providing a layered substrate for transferring;

[0030] forming a bi-layer capping coating on the substrate, each layerof coating providing protection and adhesion; and

[0031] forming a carrier assembly on the bi-layer capping coating.

[0032] The bilayer capping coating of the present invention is formed bydepositing at least two consecutive layers, hence creating a bi-layerprotecting the substrate to be transferred from negative effects ofattachment and the later removal of the carrier assembly.

[0033] The present invention also provides a method for wafer-leveltransfer that comprises the steps of:

[0034] providing a layer to be transferred on a semiconductor substrate;

[0035] forming a first layer of a capping coating on the layer to betransferred, said first layer provides adhesion and protection fromoxidation;

[0036] forming a second layer of a capping coating on said first layer,said second layer provides additional protection and adhesion to acarrier assembly;

[0037] adhering the carrier assembly to a carrier wafer by means of anadhesive; and

[0038] removing the semiconductor substrate whereby said layer to betransferred is attached to the carrier assembly.

BRIEF DESCRIPTION OF THE DRAWINGS

[0039]FIG. 1 is a schematic representation of a prior art structureincluding a single-layer capping coating.

[0040]FIG. 2 is a schematic representation of a structure of the presentinvention including a bi-layer capping coating.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0041] The present invention relates to a method for manufacturing 3 Dintegrated structures based on an assembly approach in which alayer-to-be transferred is coated with a bi-layer capping stack, apolyimide layer, and an adhesive layer. That structure is then bonded toa glass carrier-wafer and upon removal of the bulk silicon, it istransferred to a new circuit, and attached to this new circuit usingbonding techniques such as, for example, adhesive bonding. In thesubsequent step, the glass layer is released (for example, by laserablation), and the residual polyimide layer is removed by plasma ashingusing oxygen.

[0042] The aforementioned protecting capping stack is comprised of twolayers including a first layer of silicon nitride and a second layer ofan amino silane deposited over the whole area of the wafer. Such abi-layer cap provides not only protection from both Cu and oxygendiffusion, but it presents a SiCMOS-compatible and reliable solution foruse in the 3 D applications where Cu-polyimide layers are present. Thethickness of the first and second layers of the inventive bi-layercapping coating may vary depending on the conditions used for depositingeach of the layers. Typically, the SiN layer has a thickness of fromabout 100 to about 1000 nm, while the amino silane has a thickness of afew monolayers. Other thickness besides the ranges mentioned herein arealso contemplated herein

[0043] The term “amino silane” is used in the present invention todenote a compound that has the formula:

[0044] wherein R₁, R₂, R₃, R₅, and R₆, independently of each other, canbe hydrogen or an organic radical such as, for example, a lower alkylradical containing from 1 to about 6 carbon atoms, an acyl radicalcontaining 1 to 6 carbon atoms, or an allyl, alkenyl or alkynyl radicalcontaining 2 to 6 carbon atoms and R₄ can be an organic radical such as,for example, a lower alkyl containing from 1 to about 6 carbon atoms oran aromatic system such as, for example, phenyl or benzyl derivative.Illustrative examples of amino silanes that can be employed in thepresent invention as the second layer of the bi-layer capping coatinginclude, but are not limited to: 3-aminopropyl-trimethoxy silane, vinylaminomethyl triacetoxysilane, and the like. Of the aforementioned aminosilanes, it is highly preferred to use 3-aminopropyl-trimethoxy silaneas the second layer of the bi-layer capping coating of the presentinvention.

[0045] As stated above, the first layer of inventive bi-layer cappingcoating is a silicon nitride layer. The process of depositing siliconnitride is well known. Illustrative methods that can be used in thepresent invention to deposit the silicon nitride layer of the bi-layercapping coating include, for example, spin-coating, chemical vapordeposition (CVD), plasma enhanced chemical vapor deposition (PECVD),chemical solution deposition, atomic layer deposition, evaporation,physical vapor deposition (PVP), and other like deposition processes.

[0046] The silicon nitride layer of the bi-layer capping coating of thepresent invention exhibits good adhesion properties to materials used inthe back-end-of the-line (BEOL) processing, namely conductive materialssuch as Cu, and dielectric films including, for example, silicondioxide, oxide films containing phosphorus or boron, such as phosphorusdoped silicate glass (PSG), boron doped silicate glass (BSG), andboron-phosphorus doped silicate glass (BPSG), a silicon oxynitride,nitrides, and other low-k organic and non-organic films. Also siliconnitride allows for good chemical mechanical polishing (CMP) processselectivity to the aforementioned materials. Therefore, in Cu-dualdamascene structures, it is used as a CMP hard mask.

[0047] The above characteristics of silicon nitride allow thisinsulating material to be utilized as a capping layer in applications inwhich metal capping layers failed. Namely, silicon nitride can bedeposited over the surface of the to-be-transferred layer (with Cupatterned structure) followed by the amino silane deposition (formationof the bi-layer cap). Subsequently, the layer transfer steps areimplemented (deposition of polyimide adhesives, attachment of glass,removal of the bulk silicon, bonding to a new substrate, release ofglass carrier, strip of polyimide).

[0048] In embodiments wherein the silicon nitride is deposited over aninterconnect structure containing Cu metallurgy, the silicon nitrideserves as a Cu protection layer, preventing Cu oxidation. Depending onthe processing scheme, the silicon nitride layer can be easily removedby well-known wet or dry etching processes, or simply (and preferably)by a CMP process. In such a scheme, silicon nitride would serve as asacrificial layer. For other 3 D applications, the silicon nitride layercan be left on as a constituent of the structure, and it can be, forexample, used as a passivation layer or as an etch stop layer to addadditional wiring layers.

[0049] In this invention, the bi-layer capping layer is proposed forCMOS-compatible processes related to 3 D integration applications, henceit is expected that the thermal budget will not exceed 400° C. Thethermal stability of silicon nitride has been well documented for suchapplications. On the other hand, thermal stability of the aminosilane/polyimide system depends on the processing ambient. Thedegradation under nitrogen is minimal at 400° C. (16 hours), but airenriched nitrogen probably causes oxidation and decomposition ofunreacted surface amino silane.

[0050] However, the application of present invention is related topolyimide materials which have to be cured in an oxygen-free ambient.Hence, without any added restrictions the stability of the aminosilane-polyimide interface is insured. All of the above informationleads to the conclusion that silicon nitride/amino silane system is anexcellent capping bi-layer for 3 D integration applications whenCu-polyimide interfaces are involved.

[0051] The prior art structure of the assembly approach technique usedin 3 D integration applications is shown in FIG. 1. The structureconsists of: a layered structure-to-be transferred 100, which includesbulk silicon 101 and device layer 102 terminated by the Cu patternedwiring level 103; capping layer 200; sacrificial polyimide layer 300;adhesion layer 400; and glass carrier 500. In such a structure, only anamino silane, such as 3-aminopropyl-trimethoxy silane, is used as thecapping layer 200.

[0052] Amino silanes serve as adhesion promoters for patterned Si BEOLstructures enabling increased strength in the Cu-polyimide anddielectric-polyimide interfaces. In addition, amino silanes serve as Cudiffusion barriers, limiting the creation of Cu-containing precipitatesin the polyimide. However, upon plasma exposure the amino silane reducessimply to a layer of silicon oxide and electrical evaluation of thelayer transfer process using this scheme showed increased Cu wireresistivity. Hence, it has been concluded that Cu surface degradedduring the oxygen-plasma removal of the polyimide, caused by oxidationwas not prevented by the silicon oxide layer resulting from the oxidizedamino silane.

[0053] The present invention is based on a bi-layer approach, i.e., theprevious single capping layer 200 in this scheme is substituted by acapping layer 200′ which is comprised of two films: silicon nitride 201′underneath the amino silane layer 202′. The schematic diagram of theinventive structure is shown, for example, in FIG. 2. The combinedproperties of the silicon nitride 201′ (oxygen diffusion barrier layerwith good adhesion properties to BEOL materials), and amino silane layer202′ (adhesion promoter to polyimide) provides superior capping layercharacteristics.

[0054] In FIG. 2, reference numeral 100 denotes a layered substrate tobe transferred. The layered substrate 100 includes a semiconductorsubstrate 100, device layer 102 which can be terminated with a layer 103that comprises at least one metallic element such as Ti, Ta, Zr, Hf,silicides, nitrides and conducting siliconnitrides of the aforementionedelemental metals; Cu, W, Al, composites of these metals with glass; andany combination thereof. Preferably, layer 103 comprises Cu. Themetallic element of layer 103 may be patterned, i.e., a patterned wiringlevel, or a blanket layer. When a patterned metallic element is present,portions of layer 103 may be comprised of an insulating materialincluding oxides, nitrides, oxynitrides, polymeric dielectrics andinorganic dielectrics. The insulating material may be porous ornon-porous. The layered substrate 100 is fabricated using any well-knownsemiconductor processing technique.

[0055] The semiconductor substrate 101 may be a bulk semiconductorincluding, for example, Si, SiGe, SiC, SiGeC, GaAs, InP, InAs and otherIII-V compound semiconductors, II-V compound semiconductors, or layeredsemiconductors such as silicon-on-insulators (SOI), SiC-on-insulator(SiCOI) or silicon germanium-on-insulators (SGOI). When the layeredsemiconductors are employed, the top layer of those substrates representthe device layer 102.

[0056]FIG. 2 also shows an example of a carrier assembly that can beemployed in the present invention. The carrier assembly may include acarrier wafer 500, adhesion layer 400 and intermediate layer 300. Thecarrier assembly is fabricated using techniques that are well-known inthe art. For example, the carrier assembly can be formed by applying anadhesive coating atop a carrier wafer using a conventional depositionprocess such as spin-on coating, PECVD, CVD or physical vapor deposition(PVP). The intermediate layer is then applied by using one of the abovementioned deposition processes. In a preferred embodiment, the carrierassembly comprises glass and an intermediate layer of a polyimide.

[0057] Carrier wafer 500 may be comprised of a semiconductor includingany group III-V or II-V semiconductor, SOI, SGOI, alumina, ceramics andthe like. Intermediate layer 300 of the carrier assembly is anypolyimide material, which is typically used as an adhesive coating insuch a structure. Examples of polyimide materials that can be employedin the present invention include polyamic acid (PAA)-based polyimides,polyimic ester-based polyimides and pre-imidized polyimides.

[0058] Adhesion layer 400 includes coupling agents such as aminosilanes. Adhesion layer 400 serves to bond the carrier wafer 500 to theintermediate layer 300.

[0059] The 3 D structures transferred using this bi-layer (siliconnitride/amino silane) approach preserved circuit performance, indicatingthat the inventive bi-layer capping coating reliably performs itsfunction.

[0060] This invention is based on the use of the wafer-level layertransfer process which incorporates the inventive bi-layer cappingcoating described above. This type of passivation material is proposedsince it is compatible with current CMOS technology. Specifically, thewafer-level layer transfer method of the present invention includesfirst providing a layer to be transferred on a semiconductor substrateusing well known CMOS process steps. The first layer of the inventivecapping coating, e.g., silicon nitride, which provides good adhesion andprotection from oxidation for the layer to be transferred is then formedusing a conventional deposition process such as spin on coating, PECVD,CVD or PVP. Next, the second layer of the inventive capping coating,i.e., the amino silane, which serves as an additional diffusion barrierand provides adhesion to the carrier assembly is applied to the firstlayer using spin on coating, PECVD, CVD or PVP. The carrier assemblycomprising the intermediate layer attached to a carrier wafer by meansof suitable adhesive is then adhered to the second layer. After thisstep, the semiconductor substrate is removed such that the layer to betransferred is attached to the carrier assembly thus achieving layertransfer. The removal may be achieved by laser ablation or etching.

[0061] The method of the present invention may further comprise thesteps of joining an exposed surface of the transferred layer to a topsurface of a receiver substrate, and removing the carrier assembly toachieve further transfer of the transferred layer from the carrierassembly to the receiver substrate.

[0062] In this embodiment, the semiconductor and receiver substratescontain semiconductor components and the carrier assembly is used toenable the layer transfer of the semiconductor components fromsemiconductor substrate onto semiconductor components from the receiversubstrate.

[0063] The focus of this invention is on ability to integratemultifunctional 3 D structures with active and passive components bycoating their interconnecting elements with passivation layer to protectthem from degradation during the layer transfer process.

[0064] The concepts disclosed in the present invention can be used toadd functionality to the 3 D ICs without deviating from the spirit ofthe invention. For example, the methods can be applied to futureoptoelectronic device structures. In such cases, firstly the type of thematerial to create the layers can be replaced by other materials such asII-VI and 111-V materials, (example: gallium arsenide or indiumphosphide) and organic materials, and should be selected according tothe specific application however similar bi-layer passivation can beused to preserve electrical and mechanical stability of thesemiconductor elements. Secondly the functional bi-layer can be anintegral part of an optoelectronic structure, including future3-dimensional circuit stacks, allowing for integration of complexmultifunctional and mixed-technology systems or elements on a singlewafer.

[0065] While the present invention has been particularly shown anddescribed with respect to preferred embodiments, it will be understoodby those skilled in the art that the foregoing and other changes informs and details may be made without departing from the spirit andscope of the present invention. It is therefore intended that thepresent invention not be limited to the exact forms and detailsdescribed and illustrates, but fall within the scope of the appendedclaims.

We claim:
 1. A structure for interconnecting semiconductor componentscomprising: a layered substrate for transferring; a bi-layer cappingcoating on top of the substrate, each layer of said coating providesadhesion and protection; and a carrier assembly.
 2. The structureaccording to claim 1 wherein said substrate to be transferred containsat least one semiconductor component.
 3. The structure according toclaim 2 wherein said at least one semiconducting component is selectedfrom the group consisting of semiconductor devices, semiconductorcircuits, thin-film layers, passive and/or active elements,interconnecting elements, memory elements, micro-electro-mechanicalelements, optical elements, optoelectronic elements, and photonicelements.
 4. The structure according to claim 1 wherein said carrierassembly comprises a carrier wafer, an adhesive layer and anintermediate layer.
 5. The structure according to claim 1 wherein saidcarrier assembly comprises glass and an intermediate layer of polyimide.6. The structure according to claim 4 wherein said carrier wafer isselected from the group consisting of silicon, silicon-on-insulator,silicon germanium-on-insulator, alumina, quartz, group III-V or II-VIsemiconductor wafers, and ceramics.
 7. The structure according to claim1 wherein said substrate to be transferred is terminated by a layercomprising a metallic component.
 8. The structure according to claim 7wherein said metallic component is a patterned wiring level or a blanketfilm.
 9. The structure according to claim 7 wherein said metalliccomponent is selected from the group consisting Ti, Ta, Zr, Hf, theirsilicides nitrides and their conducting siliconitrides; Cu, Al,composites of these materials with glass; and combinations thereof. 10.The structure according to claim 7 wherein said capping coating providespassivation to the metallic component.
 11. The structure according toclaim 1 wherein said capping coating comprises: a first layer thatserves as a diffusion barrier, while providing adhesion to thesubstrate; and a second layer that is capable of providing adhesion tothe carrier assembly and is an additional diffusion limiting layer. 12.The structure according to claim 11 wherein said first layer comprisessilicon nitride.
 13. The structure according to claim 11 wherein saidsecond layer comprises an amino silane and is an adhesion promoter to anintermediate layer.
 14. The structure according to claim 13 wherein saidamino silane is a compound of the formula:

wherein R₁, R₂, R₃, R₅ and R₆ are, independently of each other,hydrogen, a lower alkyl radical containing from 1 to about 6 carbonatoms, an acyl radical containing 1 to 6 carbon atoms, or an allyl,alkylene or alkynyl radical containing 2 to 6 carbon atoms, and R₄ is alower alkyl containing from 1 to 6 carbon atoms or an aromatic system.15. The structure according to claim 5 wherein said polyimide materialis selected from the group consisting of polyamic acid (PAA)-basedpolyimides, polyimic ester-based polyimides, and pre-imidizedpolyimides.
 16. The structure according to claim 5 wherein said carriersubstrate comprises glass and intermediate layer of polyimide to allowfor a further release process.
 17. The structure according to claim 11wherein said first layer further serves as protection against a removalprocess of said carrier assembly.
 18. The structure according to claim17 wherein said first layer protects from an oxygen-based plasma removalprocess.
 19. A method of constructing a structure for interconnectingsemiconductor components, comprising the steps of providing a substrateto be transferred; forming a bi-layer capping coating on the substrate,each layer of said capping coating providing protection and adhesion;and forming a carrier assembly on the capping coating.
 20. The method ofclaim 19 wherein said carrier assembly is formed by: applying anadhesive coating on a top of a carrier wafer; and depositing anintermediate layer on the adhesive coating.
 21. The method of claim 19wherein said capping coating is formed by depositing at least twoconsecutive layers and hence creating a bi-layer protecting saidsubstrate to be transferred from negative effects of attachment and thelater removal processes of said carrier assembly.
 22. The method ofclaim 19 wherein said bi-layer capping is formed by: forming a firstlayer of the bi-layer capping coating for providing a barrier todiffusion and adhesion to said substrate to be transferred; and forminga second layer of bi-layer capping coating for providing adhesion tosaid carrier assembly and providing further protection againstdiffusion.
 23. The method of claim 19 wherein bi-layer capping coatingis formed by spin on coating, plasma enhanced deposition, physical orchemical vapor deposition.
 24. A method for wafer-level layer transfercomprising the steps of: providing a layer to be transferred on asemiconductor substrate; forming a first layer of a capping coating onsaid layer to be transferred, said first layer provides adhesion andprotection from oxidation; forming a second layer of the capping coatingon said first layer, said second layer provides additional protectionand adhesion to a carrier assembly; adhering said carrier assembly to acarrier wafer by bonding; and removing said semiconductor substrate suchthat said layer to be transferred is attached to said carrier assemblythereby achieving layer transfer.
 25. The method according to claim 24,further comprising the steps of joining an exposed surface of saidtransferred layer to a top surface of a receiver substrate, removingsaid carrier assembly to achieve further transfer of said transferredlayer from said carrier assembly to said receiver substrate.
 26. Themethod according to claim 25, wherein said semiconductor and receiversubstrates contain semiconductor components and said carrier assembly isused to enable the layer transfer of said semiconductor components fromthe semiconductor substrate on to the semiconductor components from thereceiver substrate.
 27. The method according to claim 26, wherein thesemiconductor and receiver substrates are selected from the groupconsisting of silicon, silicon on insulator, II-VI compounds, III-Vcompounds, alumina and quartz.
 28. The method according to claim 26,wherein said semiconducting components are selected from the groupcomprising of semiconductor devices, semiconductor circuits, thin-filmlayers, passive and active elements, interconnecting elements, memoryelements, micro-electro-mechanical elements, optical elements,optoelectronic elements, and photonic elements.
 29. The method accordingto claim 24, wherein the material of said carrier wafer is selected fromglass and quartz.
 30. The method according to claim 24, wherein saidcarrier wafer adheres to an intermediate layer made of polyimide. 31.The method according to claim 30, wherein said release process of saidcarrier wafer is based on a laser ablation process where polyimideabsorbs all the energy allowing for separation of a wafer carrier fromthe structure.
 32. The method of 24 wherein the steps are repeatednumerous times to provide a multi-level three-dimensional structure.